1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to a method for making a semiconductor read-only memory (ROM) device comprising an array of thin-film metal-oxide semiconductor field-effect transistor (MOSFET) memory cells having a silicon-on-insulator (SOI) structure.
2. Description of Related Art
Read-only memory (ROM) is a nonvolatile semiconductor memory widely used in computer and microprocessor systems for permanently storing programs and data that are repeatedly used, such as the BIOS (Basic Input/Output System, used in operating systems of personal computers). Manufacturing ROMs involves very complicated and time-consuming processes requiring costly equipment and material. Therefore, customers typically first define the data to be permanently stored in ROMs, and then provide the data to the ROM manufacturer for programming into the ROMs.
Most ROMs have identical semiconductor structures except for the data stored therein. Thus, ROM devices are typically prefabricated up to the programming stage and then stored as semi-finished products in inventories waiting for customer orders. When the customer furnishes the data, the ROM manufacturer stores the data into the semi-finished ROMs using a mask programming process. This is now the standard method in the semiconductor industry used for ROM fabrication.
In most conventional ROMs, MOSFETs are used as the memory cells for data storage. In the mask programming stage, impurities are selectively doped into specified channels of the MOSFET memory cells so to change the threshold voltage thereof and to set the MOSFET memory cells to ON/OFF states representing the storage of different binary data. The MOSFET memory cells connect to external circuits via a plurality of polysilicon-based word lines, wherein channel regions are located beneath the word lines and between each pair of adjacent bit lines. Whether a MOSFET memory cell is set to store a binary digit of "0" or "1" depends upon whether the associated channel is doped with impurities or not. If a channel is doped with impurities, the MOSFET memory cell is set to a low threshold voltage, which effectively sets the MOSFET memory cell to a permanently-ON state representing the storage of a first binary digit, such as, for example "0." Otherwise, the MOSFET memory cell is set to a high threshold voltage, which effectively sets the MOSFET memory cell to a permanently-OFF state representing the storage of a second binary digit, such as, for example "1."
A conventional MOSFET-based ROM device is shown in FIGS. 1A-1C, wherein FIG. 1A is a top view of the ROM device; FIG. 1B is a cross-sectional view of the ROM device of FIG. 1A taken along line I-I'; and FIG. 1C is a cross-sectional view of the ROM device of FIG. 1A taken along line II-II'.
As shown, the conventional ROM device includes a semiconductor substrate 10, such as a P-type silicon substrate, on which a plurality of parallel-spaced bit lines 11 and a plurality of parallel-spaced word lines 13, crossing bit lines 11, are formed. Word lines 13 are isolated from the underlying bit lines 11 using an oxidation layer 12. The conventional ROM device also includes a plurality of MOSFET memory cells, wherein each MOSFET memory cell is associated with one segment of word lines 13 between each neighboring pair of bit lines 11.
In the method for fabricating the conventional ROM device, as shown in FIG. 1C, an ion implantation process dopes an N-type impurity material, such as arsenic (As), into selected regions of substrate 10 to form a plurality of parallel-spaced diffusion regions serving as bit lines 11. The interval region between each neighboring pair of bit lines 11 serves as a channel region 16. Subsequently, a thermal oxidation process forms oxidation layer 12 over the entire top surface of the device. Next, a conductive layer, such as a highly-doped polysilicon layer, is formed over the device, and is then selectively removed through a photolithographic and etching process. The remaining portions of the conductive layer serve as word lines 13.
Upon receipt of a customer order supplying binary data, a mask programming process permanently writes the binary data into the ROM device. In the mask programming process, a mask 15 is placed over the device, wherein mask 15 is predefined to form a plurality of openings according to the bit pattern of the binary data to be written into the ROM device. The plurality of openings expose channel regions of a first selected group of MOSFET memory cells, wherein the exposed channel regions are set to a permanently-ON state. By contrast, the unexposed channel regions of a second group of the MOSFET memory cells are set to a permanently-OFF state. Subsequently, an ion implantation dopes a P-type impurity material, such as boron, into the exposed channel regions.
In the finished ROM device, the doped channel regions cause the associated MOSFET memory cells to have a low threshold voltage, and thus, sets the MOSFET memory cells to a permanently-ON state representing the permanent storage of a first binary digit, such as "0." On the other hand, the undoped channel regions cause the associated MOSFET memory cells to have a high threshold voltage, and thus, sets the MOSFET memory cells to a permanently-OFF state representing the permanent storage of a second binary digit, such as "1."
Another conventional ROM device is shown in FIGS. 2A and 2B, wherein FIG. 2A is a top view of the ROM device, and FIG. 2B is a cross-sectional view of the ROM device of FIG. 2A taken along line III-III'.
As shown in FIG. 2A, the ROM device comprises a plurality of word lines WL1, WL2, WL3 and a plurality of bit lines BL1, BL2, BL3, wherein word lines WL1, WL2, WL3 each comprise a highly-doped polysilicon layer 23 serving as a gate region for the memory cells of the ROM device. Square boxes, as indicated by reference numeral 21, that are formed in an array between the word lines represent a plurality of source/drain regions.
Referring to FIG. 2B, in the method for fabricating the conventional ROM device, an ion implantation process dopes an N-type impurity material, such as arsenic (As), into selected areas of a substrate 20 so to form a plurality of parallel N+ source/drain regions 21 in substrate 20. The undoped regions between N+ source/drain regions 21 serve as channel regions 25. Subsequently, a select number of locations of channel regions 25 associated with the ON-state memory cells of the ROM device are doped with a P-type impurity material, such as boron (B). By contrast, the undoped channel regions are associated with the OFF-state memory cells. In a subsequent step, a plurality of oxide layers 22 are formed over respective channel regions 25, and a plurality of gate layers 23 are formed over respective oxide layers 22. N+ source/drain regions 21 and gate layers 23 together comprise a base for forming an array of MOSFET memory cells thereon. A mask insulating layer 27 is subsequently formed over the entire top surface of the device and selectively is removed to form a plurality of contact windows 28 exposing N+ source/drain regions 21. A metal, such as aluminum, is filled into the contact windows 28 to form a plurality of metal plugs 26 for electrically connecting N+ source/drain regions 21 to the word lines (not shown) to be formed on metal plugs 26.
One problem with the foregoing conventional methods for making ROMs is that the mask programming process must be conducted before the fabrication of the MOSFET memory cells are complete. In other words, there are still several processes required to complete the ROM device even after a customer order is received. Consequently, the time required to complete the mask programming process and the subsequent processes is quite lengthy. This lengthens the delivery time for the ROM device and makes the ROM device produced this way less competitive in the market.
Furthermore, leakage current occurs between source/drain regions 21 and substrate 20 in the conventional ROMs, since source/drain regions are formed in substrate 20. Still another problem of conventional ROMs is that, since contact windows 28 are formed above N+ source/drain regions 21, a large area is required for formation of N+ source/drain regions 21, resulting is a ROM device that can not be made smaller for increased integration.